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Design, Automation and Test in Europe Conference and Exhibition (DATE'03)   p. 10036
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures
M. Sanchez-Elez, Universidad Complutense de Madrid
M. Fernandez, Universidad Complutense de Madrid
M. Anido, Federal University do Rio de Janeiro
H. Du, University of California at Irvine
N. Bagherzadeh, University of California at Irvine
R. Hermida, Universidad Complutense de Madrid

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10191
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Abstract
This paper presents a new technique to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. The main goal is to improve application energy consumption. Two levels of on-chip data storage are assumed in the reconfigurable architecture. The Data Scheduler attempts to optimally exploit this storage, by deciding in which on-chip memory the data have to be stored in order to reduce energy consumption. We also show that a suitable data scheduling could decrease the energy required to implement the dynamic reconfiguration of the system.
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Citation:  M. Sanchez-Elez, M. Fernandez, M. Anido, H. Du, N. Bagherzadeh, R. Hermida, "Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures," date, p. 10036,  Design, Automation and Test in Europe Conference and Exhibition (DATE'03),  2003