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Design, Automation & Test in Europe Conference & Exhibition

Mar. 3 2003 to Mar. 7 2003

Munich, Germany

ISSN: 1530-1591

ISBN: 0-7695-1870-2

Table of Contents

Synthesis of CMOS analog cells using AMIGOFull-text access may be available. Sign in or learn about subscription options.pp. 297-302 suppl.
by Ramy Iskander, Mohamed Dessouky, Maie Aly, Mahmoud Magdy, Noha Hassan, Noha Soliman, Sami Moussa
Proceedings Design, Automation and Test in Europe Conference and ExhibitionFull-text access may be available. Sign in or learn about subscription options.
IC design challenges for ambient intelligenceFull-text access may be available. Sign in or learn about subscription options.pp. 2,3,4,5,6,7
by E. Aarts, R. Roovers
Semiconductor challengesFull-text access may be available. Sign in or learn about subscription options.pp. 8
by A. Cuomo
Ambient intelligence visions and achievements: linking abstract ideas to real-world conceptsFull-text access may be available. Sign in or learn about subscription options.pp. 10,11,12,13,14,15
by M. Lindwer, D. Marculescu, T. Basten, R. Zimmennann, R. Marculescu, S. Jung, E. Cantatore
Improving the efficiency of memory partitioning by address clusteringFull-text access may be available. Sign in or learn about subscription options.pp. 18,19,20,21,22,23
by A. Macii, E. Macii, M. Poncino
A new algorithm for energy-driven data compression in VLIW embedded processorsFull-text access may be available. Sign in or learn about subscription options.pp. 24,25,26,27,28,29
by A. Macii, E. Macii, F. Crudo, R. Zafalon
Power efficiency through application-specific instruction memory transformationsFull-text access may be available. Sign in or learn about subscription options.pp. 30,31,32,33,34,35
by P. Petrov, A. Orailoglu
Low energy data management for different on-chip memory levels in multi-context reconfigurable architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 36,37,38,39,40,41
by M. Sanchez-Elez, M. Fernandez, M. Anido, H. Du, N. Bagherzadeh, R. Hermida
Circuit and platform design challenges in technologies beyond 90nmFull-text access may be available. Sign in or learn about subscription options.pp. 44,45,46,47
by B. Grundmann, R. Galivanche, S. Kundu
Global wire bus configuration with minimum delay uncertaintyFull-text access may be available. Sign in or learn about subscription options.pp. 50,51,52,53,54,55
by Li-Da Huang, Hung-Ming Chen, D.F. Wong
Timing verification with crosstalk for transparently latched circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 56,57,58,59,60,61
by Hai Zhou
Statistical timing analysis using bounds [IC verification]Full-text access may be available. Sign in or learn about subscription options.pp. 62,63,64,65,66,67
by A. Agarwal, D. Blaauw, V. Zolotov, S. Vrudhula
Reduced delay uncertainty in high performance clock distribution networksFull-text access may be available. Sign in or learn about subscription options.pp. 68,69,70,71,72,73
by D. Velenis, M.C. Papaefthymiou, E.G. Friedman
Scaling into ambient intelligenceFull-text access may be available. Sign in or learn about subscription options.pp. 76,77,78,79,80,81
by T. Basten, L. Benini, A. Chandrakasan, M. Lindwer, Jie Liu, Rex Min, Feng Zhao
Masking the energy behavior of DES encryption [smart cards]Full-text access may be available. Sign in or learn about subscription options.pp. 84,85,86,87,88,89
by H. Saputra, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, R. Brooks, S. Kim, W. Zhang
Scheduling and mapping of conditional task graphs for the synthesis of low power embedded systemsFull-text access may be available. Sign in or learn about subscription options.pp. 90,91,92,93,94,95
by Dong Wu, B.M. Al-Hashimi, P. Eles
Synthesis of application-specific highly-efficient multi-mode systems for low-power applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 96,97,98,99,100,101
by Lih-Yih Chiou, S. Bhunia, K. Roy
Virtual compression through test vector stitching for scan based designsFull-text access may be available. Sign in or learn about subscription options.pp. 104,105,106,107,108,109
by Wenjing Rao, A. Orailoglu
Test pattern compression using prelude vectors in fan-out scan chain with feedback architectureFull-text access may be available. Sign in or learn about subscription options.pp. 110,111,112,113,114,115
by Nahmsuk Oh, R. Kapur, T.W. Williams, J. Sproch
A technique for high ratio LZW compression [logic test vector compression]Full-text access may be available. Sign in or learn about subscription options.pp. 116,117,118,119,120,121
by M.J. Knieser, F.G. Wolff, C.A. Papachristou, D.J. Weyer, D.R. McIntyre
Fast computation of data correlation using BDDsFull-text access may be available. Sign in or learn about subscription options.pp. 122,123,124,125,126,127
by Zhihong Zeng, Qiushuang Zhang, I. Harris, M. Ciesielski
RTOS modeling for system level designFull-text access may be available. Sign in or learn about subscription options.pp. 130,131,132,133,134,135
by A. Gerstlauer, Haobo Yu, D.D. Gajski
Modeling and integration of peripheral devices in embedded systemsFull-text access may be available. Sign in or learn about subscription options.pp. 136,137,138,139,140,141
by Shaojie Wang, S. Malik, R.A. Bergamaschi
Systematic embedded software generation from SystemCFull-text access may be available. Sign in or learn about subscription options.pp. 142,143,144,145,146,147
by F. Herrera, H. Posadas, P. Sanchez, E. Villar
Noise macromodel for radio frequency integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 150,151,152,153,154,155
by Yang Xu, Xin Li, Peng Li, L. Pileggi
Approximation approach for timing jitter characterization in circuit simulatorsFull-text access may be available. Sign in or learn about subscription options.pp. 156,157,158,159,160,161
by M.M. Gourary, S.G. Rusakov, S.L. Ulyanov, M.M. Zharov, K.K. Gullapalli, B.J. Mulvaney
A model of computation for continuous-time /spl Delta//spl Sigma/ modulatorsFull-text access may be available. Sign in or learn about subscription options.pp. 162,163,164,165,166,167
by E. Martens, G. Gielen
Behavioural modelling and simulation of /spl Sigma//spl Delta/ modulators using hardware description languagesFull-text access may be available. Sign in or learn about subscription options.pp. 168,169,170,171,172,173
by R. Castro-Lopez, F.V. Ferandez, F. Medeiro, A. Rodriguez-Vazquez
Securing mobile appliances: new challenges for the system designerFull-text access may be available. Sign in or learn about subscription options.pp. 176,177,178,179,180,181
by A. Raghunathan, S. Ravi, S. Hattangady, J.-J. Quisquater
Schedulability analysis and optimization for the synthesis of multi-cluster distributed embedded systemsFull-text access may be available. Sign in or learn about subscription options.pp. 184,185,186,187,188,189
by P. Pop, P. Eles, Zebo Peng
A general framework for analysing system properties in platform-based embedded system designsFull-text access may be available. Sign in or learn about subscription options.pp. 190,191,192,193,194,195
by S. Chakraborty, S. Kunzli, L. Thiele
Exact high level WCET analysis of synchronous programs by symbolic state space explorationFull-text access may be available. Sign in or learn about subscription options.pp. 196,197,198,199,200,201,202,203
by G. Logothetis, K. Schneider
Rapid prototyping of flexible embedded systems on multi-DSP architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 204,205,206,207,208,209
by B. Rinner, M. Schmid, R. Weiss
DFT for testing high-performance pipelined circuits with slow-speed testersFull-text access may be available. Sign in or learn about subscription options.pp. 212,213,214,215,216,217
by M. Nummer, M. Sachdev
Extending JTAG for testing signal integrity in SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 218,219,220,221,222,223
by N. Ahmed, M. Tehranipour, M. Nourani
EBIST: a novel test generator with built-in fault detection capabilityFull-text access may be available. Sign in or learn about subscription options.pp. 224,225,226,227,228,229
by D.K. Pradhan, Chunsheng Liu, K. Chakraborty
A partition-based approach for identifying failing scan cells in scan-BIST with applications to system-on-chip fault diagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 230,231,232,233,234,235
by Chunsheng Liu, K. Chakrabarty
Time-varying, frequency-domain modeling and analysis of phase-locked loops with sampling phase-frequency detectorsFull-text access may be available. Sign in or learn about subscription options.pp. 238,239,240,241,242,243
by P. Vanassche, G. Gielen, W. Sansen
A new simulation technique for periodic small-signal analysisFull-text access may be available. Sign in or learn about subscription options.pp. 244,245,246,247,248,249
by M.M. Gourary, S.G. Rusakov, S.L. Ulyanov, M.M. Zharov
Generalized posynomial performance modelingFull-text access may be available. Sign in or learn about subscription options.pp. 250,251,252,253,254,255
by T. Eeckelaert, W. Daems, G. Gielen, W. Sansen
Holmes: capturing the yield-optimized design space boundaries of analog and RF integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 256,257,258,259,260,261
by B. De Smedt, G. Gielen
High-level allocation to minimize internal hardware wastage [high-level synthesis]Full-text access may be available. Sign in or learn about subscription options.pp. 264,265,266,267,268,269
by M.C. Molina, J.M. Mendias, R. Hermida
Dynamic conditional branch balancing during the high-level synthesis of control-intensive designsFull-text access may be available. Sign in or learn about subscription options.pp. 270,271,272,273,274,275
by S. Cupta, N. Dutt, R. Gupta, A. Nicolau
Distributed synchronous control units for dataflow graphs under allocation of telescopic arithmetic unitsFull-text access may be available. Sign in or learn about subscription options.pp. 276,277,278,279,280,281
by E. Kim, H. Saito, Jeong-Gun Lee, Dong-Ik Lee, H. Nakamura, T. Nanya
Automated bus generation for multiprocessor SoC designFull-text access may be available. Sign in or learn about subscription options.pp. 282,283,284,285,286,287
by Kyeong Keol Ryu, V.J.I.I.I. Mooney
Online scheduling for block-partitioned reconfigurable devicesFull-text access may be available. Sign in or learn about subscription options.pp. 290,291,292,293,294,295
by H. Walder, M. Platzner
Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 296,297,298,299,300,301
by Bingfeng Mei, S. Vernalde, D. Verkest, H. De Man, R. Lauwereins
Virtual hardware byte code as a design platform for reconfigurable embedded systemsFull-text access may be available. Sign in or learn about subscription options.pp. 302,303,304,305,306,307
by S. Lange, U. Kebschull
A method of test generation for path delay faults using stuck-at fault test generation algorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 310,311,312,313,314,315
by S. Ohtake, K. Ohtani, H. Fujiwara
A novel, low-cost algorithm for sequentially untestable fault identificationFull-text access may be available. Sign in or learn about subscription options.pp. 316,317,318,319,320,321
by M. Syal, M.S. Hsiao
Non-enumerative path delay fault diagnosis [logic testing]Full-text access may be available. Sign in or learn about subscription options.pp. 322,323,324,325,326,327
by S. Padmanaban, S. Tragoudas
Delay defect diagnosis based upon statistical timing models - the first step [logic testing]Full-text access may be available. Sign in or learn about subscription options.pp. 328,329,330,331,332,333
by A. Krstic, L.-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, M.S. Abadir
Introduction to hardware abstraction layers for SoCFull-text access may be available. Sign in or learn about subscription options.pp. 336,337
by Sungjoo Yoo, A.A. Jerraya
Hardware/software partitioning of operating systems [SoC applications]Full-text access may be available. Sign in or learn about subscription options.pp. 338,339
by V.J. Mooney
Embedded software in digital AM-FM chipsetFull-text access may be available. Sign in or learn about subscription options.pp. 340,341
by M. Sarlotte, B. Candaele, J. Quevremont, D. Merel
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chipFull-text access may be available. Sign in or learn about subscription options.pp. 350,351,352,353,354,355
by E. Rijpkema, K.G.W. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, E. Waterlander
Communication centric architectures for turbo-decoding on embedded multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 356,357,358,359,360,361
by F. Gilbert, M.J. Thul, N. Wehn
Development and application of design transformations in ForSyDe [high level synthesis]Full-text access may be available. Sign in or learn about subscription options.pp. 364,365,366,367,368,369
by I. Sander, A. Jantsch, Zhonghai Lu
System level specification in LavaFull-text access may be available. Sign in or learn about subscription options.pp. 370,371,372,373,374,375
by S. Singh
Formal semantics of synchronous SystemCFull-text access may be available. Sign in or learn about subscription options.pp. 376,377,378,379,380,381
by A. Salem
Introspection in system-level language frameworks: meta-level vs. integratedFull-text access may be available. Sign in or learn about subscription options.pp. 382,383,384,385,386,387
by F. Doucet, S. Shukla, R. Gupta
SystemC-AMS requirements, design objectives and rationaleFull-text access may be available. Sign in or learn about subscription options.pp. 388,389,390,391,392,393
by A. Vachoux, C. Grimm, K. Einwich
Parallel processing architectures for reconfigurable systemsFull-text access may be available. Sign in or learn about subscription options.pp. 396,397
by K.A. Vissers
Different approaches to add reconfigurability in a SoC architectureFull-text access may be available. Sign in or learn about subscription options.pp. 398
by B. Gupta, M. Borgatti
A lightweight approach for embedded reconfiguration of FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 399,400
by B. Blodget, S. McMillan, P. Lysaght
Creating value through testFull-text access may be available. Sign in or learn about subscription options.pp. 402,403,404,405,406,407
by E.J. Marinissen, B. Vermeulen, R. Madge, M. Kessler, M. Muller
Control flow driven splitting of loop nests at the source code levelFull-text access may be available. Sign in or learn about subscription options.pp. 410,411,412,413,414,415
by H. Falk, P. Marwedel
Data space oriented scheduling in embedded systemsFull-text access may be available. Sign in or learn about subscription options.pp. 416,417,418,419,420,421
by M. Kandemir, G. Chen, W. Zhang, I. Kolcu
Compiler-directed ILP extraction for clustered VLIW/EPIC machines: predication, speculation and modulo schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 422,423,424,425,426,427
by S. Pillai, M.F. Jacome
An efficient hash table based approach to avoid state space explosion in history driven quasi-static schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 428,429,430,431,432,433
by A.G. Lomena, M. Lopez-Vallejo, Y. Watanabe, A. Kondratyev
Time budgeting in a wireplanning contextFull-text access may be available. Sign in or learn about subscription options.pp. 436,437,438,439,440,441
by J. Westra, D.-J. Jongeneel, R.H.J.M. Otten, C. Visweswariah
Interconnect planning with local area constrained retiming [logic IC layout]Full-text access may be available. Sign in or learn about subscription options.pp. 442,443,444,445,446,447
by Ruibing Lu, Cheng-Kok Koh
A novel metric for interconnect architecture performanceFull-text access may be available. Sign in or learn about subscription options.pp. 448,449,450,451,452,453
by P. Dasgupta, A.B. Kahng, S. Muddu
Specification of non-functional intellectual property componentsFull-text access may be available. Sign in or learn about subscription options.pp. 456,457,458,459,460,461
by Jianwen Zhu, Wai Sum Mong
Profile-driven selective code compression [embedded systems]Full-text access may be available. Sign in or learn about subscription options.pp. 462,463,464,465,466,467
by Yuan Xie, W. Wolf, H. Lekatsas
Design and analysis of a programmable single-chip architecture for DVB-T base-band receiverFull-text access may be available. Sign in or learn about subscription options.pp. 468,469,470,471,472,473
by Chengzhi Pan, N. Bagherzadeh, A.H. Kamalizad, A. Koohi
Panel title: reconfigurable computing-different perspectivesFreely available from IEEE.pp. 476-476
by W. Rosenstiel, R. Lauwereins, I. Bolsens, C. Rowen, Y. Tanurhan, K. Vissers, S. Wang
RF-BIST: loopback spectral signature analysisFull-text access may be available. Sign in or learn about subscription options.pp. 478,479,480,481,482,483
by D. Lupea, U. Pursche, H.-J. Jentschel
Optimizing stresses for testing DRAM cell defects using electrical simulationFull-text access may be available. Sign in or learn about subscription options.pp. 484,485,486,487,488,489
by Z. Al-Ars, A.J. van de Goor, J. Braun, D. Richter
On modeling cross-talk faults [VLSI circuits]Full-text access may be available. Sign in or learn about subscription options.pp. 490,491,492,493,494,495
by S. Zachariah, Yi-Shing Chang, S. Kundu, C. Tirumurti
Techniques for automatic on chip closed loop transfer function monitoring for embedded charge pump phase locked loopsFull-text access may be available. Sign in or learn about subscription options.pp. 496,497,498,499,500,501
by M.J. Burbidge, J. Tijou, A. Richardson
Pre-characterization free, efficient power/performance analysis of embedded and general purpose software applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 504,505,506,507,508,509
by V.S.R. Rapaka, D. Marculescu
Runtime code parallelization for on-chip multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 510,511,512,513,514,515
by M. Kandemir, W. Zhang, M. Karakoy
SDRAM-Energy-Aware memory allocation for dynamic multi-media applications on multi-processor platformsFull-text access may be available. Sign in or learn about subscription options.pp. 516,517,518,519,520,521
by P. Marchal, D. Bruni, J.I. Gomez, L. Benini, L. Pinuel, F. Catthoor, H. Corporaal
Modeling and evaluation of substrate noise induced by interconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 524,525,526,527,528,529
by F. Martorell, D. Mateo, X. Aragones
Model-order reduction based on Prony's methodFull-text access may be available. Sign in or learn about subscription options.pp. 530,531,532,533,534,535
by M.M. Mansour, A. Mehrotra
Combined FDTD/macromodel simulation of interconnected digital devicesFull-text access may be available. Sign in or learn about subscription options.pp. 536,537,538,539,540,541
by S. Grivet-Talocia, I.S. Stievano, I.A. Maio, F.G. Canavero
Building fast and accurate SW simulation models based on hardware abstraction layer and simulation environment abstraction layerFull-text access may be available. Sign in or learn about subscription options.pp. 550,551,552,553,554,555
by Sungjoo Yoo, I. Bacivarov, A. Bouchhima, Y. Paviot, A.A. Jerraya
Flexible and formal modeling of microprocessors with application to retargetable simulationFull-text access may be available. Sign in or learn about subscription options.pp. 556,557,558,559,560,561
by Wei Qin, S. Malik
Instruction set emulation for rapid prototyping of SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 562,563,564,565,566,567
by J. Schnerr, G. Haug, W. Rosenstiel
Hardware/software design space exploration for a reconfigurable processorFull-text access may be available. Sign in or learn about subscription options.pp. 570,571,572,573,574,575
by A. La Rosa, L. Lavagno, C. Passerone
From C programs to the configure-execute modelFull-text access may be available. Sign in or learn about subscription options.pp. 576,577,578,579,580,581
by J.M.P. Cardoso, M. Weinhardt
FPGA-based implementation of a serial RSA processorFull-text access may be available. Sign in or learn about subscription options.pp. 582,583,584,585,586,587
by A. Mazzeo, L. Romano, G.P. Saggese, N. Mazzocca
Optimal reconfiguration functions for column or data-bit built-in self-repairFull-text access may be available. Sign in or learn about subscription options.pp. 590,591,592,593,594,595
by M. Nicolaidis, N. Achouri, S. Boutobza
Versatile high-level synthesis of self-checking datapaths using an on-line testability metricFull-text access may be available. Sign in or learn about subscription options.pp. 596,597,598,599,600,601
by P. Oikonomakos, M. Zwolinski, B.M. Al-Hashimi
An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 602,603,604,605,606,607
by M. Rebaudengo, M.S. Reorda, M. Violante
High speed and highly testable parallel two-rail code checkerFull-text access may be available. Sign in or learn about subscription options.pp. 608,609,610,611,612,613
by M. Omana, D. Rossi, C. Metra
Safe automotive software developmentFull-text access may be available. Sign in or learn about subscription options.pp. 616,617,618,619,620,621
by K. Tindell, H. Kopetz, F. Wolf, R. Ernst
Analysis and white-box modeling of weakly nonlinear time-varying circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 624,625,626,627,628,629
by P. Dobrovolny, G. Vandersteen, P. Wambacq, S. Donnay
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