| Abstract |
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Boolean equivalence checking has turned out to be a powerful method for verifying combinational circuits and is already an integrated part of the design cycle. If equivalence checking fails, Design Error Diagnosis and Correction (DEDC) are performed. DEDC tries to locate and correct design errors fully automatically and can therefore considerably speed up the whole design cycle.
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 Additional Information
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Citation:
Dirk W. Hoffmann, Thomas Kropf,
"Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits,"
date,
p. 758,
Design, Automation and Test in Europe (DATE '00),
2000
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