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Published Articles >> Table of Contents >> Abstract
Design, Automation and Test in Europe (DATE '00)
p. 146
Design and Test Space Exploration of Transport-Triggered Architectures
V.A. Zivkovic, University of Twente
R.J.W.T. Tangelder, University of Twente
H.G. Kerkhoff, University of Twente
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840031
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| Abstract |
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This paper describes a new approach in the high level design and test of transport-triggered architectures (TTA), a special type of application specific instruction processors (ASIP). The proposed method introduces the test as an additional constraint, besides throughput and circuit area. The method, that calculates the testability of the system, helps the designer to assess the obtained architectures with respect to test, area and throughput in the early phase of the design and selects the most suitable one. In order to create the templated TTA, the "MOVE" framework has been addressed. The approach is validated with respect to the "Crypt" Unix application.
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 Additional Information
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Citation:
V.A. Zivkovic, R.J.W.T. Tangelder, H.G. Kerkhoff,
"Design and Test Space Exploration of Transport-Triggered Architectures,"
date,
p. 146,
Design, Automation and Test in Europe (DATE '00),
2000
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