Illegal State Space Identification for Sequential Circuit Test Generation

M. Konijnenburg; J. Van der Linden; A. van de Goor

doi:10.1109/DATE.1999.761213

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Design, Automation & Test in Europe Conference & Exhibition

Illegal State Space Identification for Sequential Circuit Test Generation

Year: 1999, Pages: 741

DOI Bookmark: 10.1109/DATE.1999.761213

Authors

M. Konijnenburg, Delft University of Technology
J. Van der Linden, Delft University of Technology
A. van de Goor, Delft University of Technology

Abstract

Techniques and data-structures are proposed to expand the known Global Illegal State (GIS) space, in order to reduce the search space of sequential circuit test generation.The techniques use the known GISes to generate candidate GISes, which have to be proven unjustifiable. This improves STPG performance by reducing the number of stored GISes, while covering a larger part of the GIS space.

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