Abstract
In this paper we present an efficient technique to reduce the power dissipation in a technology mapped CMOS sequential circuit based on logic and structural transformations. The power reduction is achieved by adding sequential redundancies from low switching activity gates to high switching activity gates such that the switching activities at the output of the connected to gates are significantly reduced. We show that the power reducing transformations result in a circuit that is a valid replacement of the original. The notion of validity used here is that of a delay safe replacement, i.e., the original circuit and the transformed circuit cannot be distinguished by observing the input and output behavior as long as the transformed circuit is clocked a finite number of cycles before applying any useful inputs. The potential transformations are found by direct logic implications applied to the circuit netlist. Therefore the complexity of each individual transformation is polynomial in the size of the circuit, allowing the processing of large designs.