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Published Articles >> Table of Contents >> Abstract
2003 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR '03) - Volume 1
p. 203
Video-Rate Stereo Depth Measurement on Programmable Hardware
Ahmad Darabiha, University of Toronto
Jonathan Rose, University of Toronto
W. James MacLean, University of Toronto
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CVPR.2003.1211355
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| Abstract |
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This paper describes the implementation of a stereo depth measurement algorithm in hardware on Field-Programmable Gate Arrays (FPGAs). This system generates 8-bit sub-pixel disparities on 256 by 360 pixel images at video rate (30 frames/sec). The algorithm implemented is a multi-resolution, multi-orientation phase-based technique called Local Weighted Phase-Correlation [12]. Hardware implementation speeds up the performance more than 300 times that of the same algorithm running in software. In this paper, we describe the programmable hardware platform, the base stereo vision algorithm and the design of the hardware. We include various trade-offs required to make the hardware small enough to fit on our system and fast enough to work at video rate. We also show sample outputs from the functioning hardware. Although this paper is specifically focused on phase-based stereo vision FPGA realizations, most of the design issues are common to other DSP and Vision applications.
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Citation:
Ahmad Darabiha, Jonathan Rose, W. James MacLean,
"Video-Rate Stereo Depth Measurement on Programmable Hardware,"
cvpr,
p. 203,
2003 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR '03) - Volume 1,
2003
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