|
Published Articles >> Table of Contents >> Abstract
27th Annual International Computer Software and Applications Conference
p. 466
Rapid Verification of Embedded Systems Using Patterns
W. T. Tsai, Arizona State University
L. Yu, Arizona State University
F. Zhu, University of Minnesota
R. Paul, Department of Defense
Full Article Text:
  
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CMPSAC.2003.1245381
Send link to a friend
| Abstract |
|
Verification pattern (VP) is a new technique to test embedded systems rapidly, and it has been used to test industrial safety-critical embedded systems successfully. The key concept of this approach is to classify system scenarios into patterns, and use the same code template to test all the scenarios of the same pattern. In this way, testing effort can be greatly reduced. This paper extends VPs so that they can fully interoperate with a formalized scenario model ACDATE. In this way, various static and dynamic analyses can be performed on system scenarios as well as on system patterns. Furthermore, this paper provides a mapping from system scenarios into temporal logic expressions. In this way, a practitioner can specify system constraints in scenarios, and follow the mapping to obtain the temporal logic expressions easily to perform formal model checking. This paper also provides an OO framework to support automated test script development from VPs. In this way, VPs can be used in an integrated process where both semi-formal analyses and formal techniques can be used together to develop mission-critical embedded applications.
|
 Additional Information
|
Index Terms- Verification patterns, verification, testing,
model checking, embedded systems
Citation:
W. T. Tsai, L. Yu, F. Zhu, R. Paul,
"Rapid Verification of Embedded Systems Using Patterns,"
compsac,
p. 466,
27th Annual International Computer Software and Applications Conference,
2003
|
|
