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Published Articles >> Table of Contents >> Abstract
International Symposium on Code Generation and Optimization (CGO'04)
p. 15
Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture
Chi-Keung Luk, Intel Corporation
Robert Muth, Intel Corporation
Harish Patil, Intel Corporation
Robert Cohn, Intel Corporation
Geoff Lowney, Intel Corporation
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CGO.2004.1281660
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| Abstract |
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Ispike is post-link optimizer developed for the Intel®Itanium Processor Family (IPF) processors. The IPF architecture poses both opportunities and challenges to post-link optimizations. IPF offers a rich set of performance counters to collect detailed profile information at a low cost, which is essential to post-link optimization being practical. At the same time, the prediction and bundling features on IPF make post-link code transformation more challenging than on other architectures. In Ispike, we have implemented optimizations like code layout, instruction prefetching, data layout, and data prefetching that exploit the IPF advantages, and strategies that cope with the IPF-specific challenges. Using SPEC CINT2000 as benchmarks, we show that Ispike improves performance by as much as 40% on the Itanium®2 processor, with average improvement of 8.5% and 9.9% over executables generated by the Intel®Electron compiler and by the Gcc compiler, respectively. We also demonstrate that statistical profiles collected via IPF performance counters and complete profiles collected via instrumentation produce equal performance benefit, but the profiling overhead is significantly lower for performance counters.
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Citation:
Chi-Keung Luk, Robert Muth, Harish Patil, Robert Cohn, Geoff Lowney,
"Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture,"
cgo,
p. 15,
International Symposium on Code Generation and Optimization (CGO'04),
2004
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