Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors

Abhijit Prasad; D. M. H Walker

doi:10.1109/DFTVS.2003.1250105

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems

Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors

Year: 2003, Pages: 140

DOI Bookmark: 10.1109/DFTVS.2003.1250105

Authors

Abhijit Prasad, Texas A&M University
D. M. H Walker, Texas A&M University

Abstract

The International Technology Roadmap for Semiconductors projects that IDDQ levels will rise rapidly with each technology node. In addition, manufacturing variations in the IDDQ level will be difficult to control. The combination will make it increasingly difficult to distinguish defect-free from defective chips via IDDQ tests. Built-in current sensors (BICSs) have been proposed to increase test resolution by virtually partitioning the supply mesh, so that each partition has a relatively small defect-free IDDQ level. In the future such a scheme would require 100,000 or more BICSs and thus the partitioning task needs to be automated. This paper presents a practical methodology to do this power supply partitioning.

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Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors

Authors

Abstract

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