Abstract
The voltage difference on bit line pairs is a critical parameter while designing Static Random Access Memory (SRAM). In this paper, measurement unit is presented for sampling and amplifying the weak signals of bit line pairs to higher voltage differential level. According to the measured result, the reliability analysis can be easily completed through curve fitting. The proposed circuit is designed and simulated with a 1K-bit SRAM by using a 0.18um 1P6M CMOS process. The measured results offer designers a meaningful clue to verify/strengthen their memory design.