Abstract
In this paper, a transparency paths constructing approach based on the gate-level netlist of cores is proposed. It searches the potential transparency paths using greedy searching strategy with FB-numbers as its heuristic information, and solves constraints and inconsistency by inserting basic cells, multiplexers and controlling gates. With these transparency paths, IP cores can transfer one test from their inputs to outputs per clock cycle consecutively and thus can be used in transparency-based test scheme to enable at-speed testing and decrease the overhead of dedicated wrappers and TAMs. This approach can implement Min(m,n) transparency paths for Min(m,n) Pis or POs at least, where m and n are the numbers of inputs and outputs of the core respectively.