A BIST methodology for at-speed testing of data communications transceivers

S.L. Lin; S. Mourad; S. Krishnan

doi:10.1109/ATS.2000.893628

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Proceedings of the Ninth Asian Test Symposium

A BIST methodology for at-speed testing of data communications transceivers

Year: 2000, Pages: 216

DOI Bookmark: 10.1109/ATS.2000.893628

Authors

S.L. Lin, Intelligent Micro Inc., San Jose, CA, USA
S. Mourad, Intelligent Micro Inc., San Jose, CA, USA
S. Krishnan, Intelligent Micro Inc., San Jose, CA, USA

Abstract

This paper discusses a new BIST methodology suitable for functional testing of transceivers on a data communications chip. Practical circuits are presented which allow the at-speed resting of various functional blocks. The concept has been applied to test a 400 Mbps 3-port IEEE 1394a system. The silicon for the 0.35 /spl mu/m CMOS implementation is expected in early 2001.

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