Abstract
This paper presents a quiescent current-based (IDDQ) approach for testing input/output resources in SRAM-based FPGAs. Input/output resources include input/output blocks (IOBs) and the I/O interconnect. Test generation and application strategies are proposed by taking into account the limited controllability of the I/O resources. Configuration of these resources requires that the test stimuli must be provided by internal (logic and routing) resources. A detailed presentation for testing the I/O resources of the Xilinx XC4000 family is given.