Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories

Many march tests have already been designed to cover faults of different fault models. The complexity of these tests arises when linked faults are taken into consideration.This paper presents a methodology to design tests for linked faults, resulting in the march tests: March LA, LA-, LAD and LADD-. They allow for the detection of any number of simple and linked faults. Different tests are proposed for SRAMs and DRAMs; i.e., the tests are shown to be memory technology dependent. These new tests are more efficient and offer a higher fault coverage than comparable existing tests.