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Seventh Asian Test Symposium (ATS'98)   p. 46
Alleviating DFT Cost Using Testability Driven HLS
M.L. Flottes, Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
R. Pires, Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
B. Rouzeyre, Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741582
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Abstract
This paper presents a method to carry out the register allocation phase of High Level Synthesis with testability considerations. Testability problems are identified and eliminated during this step turning testability/area trade-off to account. It allows to decrease the cost related to the application of low-level DFT techniques.
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Citation:  M.L. Flottes, R. Pires, B. Rouzeyre, "Alleviating DFT Cost Using Testability Driven HLS," ats, p. 46,  Seventh Asian Test Symposium (ATS'98),  1998