Abstract
This paper presents a test technique for CMOS operational amplifier based on the monitoring of some selected DC nodes' voltages and branches' currents. A realistic method for determining data tolerance bands due to the foundry process fluctuations of DC branches' currents and nodes' voltages of the OA is described. Optimization of the bounds for the fault detection problem is also possible by choosing carefully some design parameters like supply voltage or transistors' sizes. The efficiency of this technique has been proved by fault simulation when considering a fault model based on catastrophic defects of the transistors' connections.