Abstract
The design of a CMOS standard-cell Quasi-Delay-Insensitive (QDI) 16-bit asynchronous microprocessor is presented. ASPRO-216 is being developed for embedded applications. It is a scalar processor which issues instructions in-order and completes their execution out-of-order, and it can be customized both at the hardware and software levels to fit specific application requirements. Its architecture extensively uses an overlapping pipelined execution scheme involving de-synchronized units. The design flow and circuit style are an original application of A. Martin's method. The expected performance is 200 peak MIPS, 0.5 Watt using a 0.25 ?m technology.