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Published Articles >> Table of Contents >> Abstract
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)
p. 269
A High Speed and Low Power Phase-Frequency Detector and Charge - pump
Won - Hyo Lee, Sungkyunkwan Univ., Korea
Jun - Dong Cho, Sungkyunkwan Univ., Korea
Sung - Dae Lee, Ansan Technical College, Korea
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.760011
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| Abstract |
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In this paper, we introduce a high-speed and low
power Phase-Frequency Detector (PFD) that is designed using
modified TSPC (True Single-Phase Clock) positive edge
triggered D flip-flop. This PFD has a simpler structure with
using only 19 transistors. The operation range of this PFD is
over 1.2Ghz without additional prescaler circuits. Furthermore,
the PFD has a dead zone less than 0.01ns in the phase
characteristics and has low phase sensitivity errors. The phase
and frequency error detection range is not limited as in the case
of the pt-type and nc-type PFDs. Also, the PFD is
independent from the duty cycle of input signals. A new
charge-pump circuit is presented that is designed using a
charge-amplifier. A stand - by current enhances the speed of
charge - pump and removes the charge - sharing which causes
a phase noise in the charge - pump PLL. Also, the effects of
clock feed - through are reduced by separating the output stage
from UP and down signal. The simulation results base on a
third - order PLL are presented to verify the lock - in process
with the proposed PFD and Charge - pump circuits. The PFD
and charge - pump circuits are designed using 0.8 µm CMOS
technology with 5V supply voltage.
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 Additional Information
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Citation:
Won - Hyo Lee, Jun - Dong Cho, Sung - Dae Lee,
"A High Speed and Low Power Phase-Frequency Detector and Charge - pump,"
asp-dac,
p. 269,
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99),
1999
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