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Published Articles >> Table of Contents >> Abstract
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)
p. 117
A New Single-Clock Flip-Clop for Half-Swing Clocking
Young-Su Kwon, KAIST, Korea
Bong-il Park, KAIST, Korea
In-Cheol Park, KAIST, Korea
Chong-Min Kyung, KAIST, Korea
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759727
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| Abstract |
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We propose a new flip-flop configuration
which saves about 60% of total clocking power
using a half-swing clock. To use the half-swing clock,
level converters or special clock drivers are traditionally
required and the power consumptions of these
logic cannot be ignored. In the proposed scheme,
only NMOSes are clocked with half-swing clock in order
to make it operate without the level converter or
any other additional logics, and the random logic circuits
except clock and flip-flops are supplied by V{cc}
while the clock network is supplied by V{cc}/2. Compared
to the conventional scheme, a great amount of
power consumed in clocking which responsible for
a large portion of total chip power can be saved with
the proposed new flip-flop configuration.
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 Additional Information
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Citation:
Young-Su Kwon, Bong-il Park, In-Cheol Park, Chong-Min Kyung,
"A New Single-Clock Flip-Clop for Half-Swing Clocking,"
asp-dac,
p. 117,
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99),
1999
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