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Published Articles >> Table of Contents >> Abstract
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)
p. 93
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance
Jinsong Hou, Tsinghua Univ., Beijing
Zeyi Wang, Tsinghua Univ., Beijing
Xianlong Hong, Tsinghua Univ., Beijing
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759719
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| Abstract |
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In VLSI circuits with deep sub-micron, the
parasitic capacitance from interconnect is a very important
factor determining circuit performances such as power and
time-delay. The Boundary Element Method(BEM) is an
effective tool for solving Laplacian's equation applied in
the parasitic capacitance extraction. In this paper, a
hierarchical h-adaptive BEM is presented. It constructs a
3-D linear hierarchical shape function based on constant
boundary element and uses previous computations and
solutions. Hence, it reduces much computation in
adaptive procedure. Besides, a combination of residual-type
estimator and reduced Z-Z error estimator for more
reliable and efficient estimation of error is presented.
Some numerical results show that this method is effective.
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 Additional Information
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Index Terms- Parasitic Capacitance, Boundary Element Method, Hierarchical h-Adaptive Computation, VLSI
Citation:
Jinsong Hou, Zeyi Wang, Xianlong Hong,
"The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance,"
asp-dac,
p. 93,
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99),
1999
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