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Published Articles >> Table of Contents >> Abstract
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)
p. 41
Motion Estimator LSI for MPEG2 High Level Standard
Li Jiang, Tokyo Institute of Technology, Tokyo
Dongju Li, Tokyo Institute of Technology, Tokyo
Shintaro Haba, Tokyo Institute of Technology, Tokyo
Chawalit Honsawek, Tokyo Institute of Technology, Tokyo
Hiroaki Kunieda, Tokyo Institute of Technology, Tokyo
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759705
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| Abstract |
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In this design, a dedicated motion estimation LSI
of MPEG2 is presented. Combining our bits truncation
adaptive pyramid (BTAP) algorithm with
Window-MSPA architecture as well as by using custom
cell and full custom design methods, the chip
size becomes 4.8mm x 4.8mm small with 0.5u 2-level
metal CMOS technology. The test chip which
works at 41.5 MHz, possesses a search ranges of μ67
for image size of 1920 x 1152 and achieves video
rate of 30 field/s.
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 Additional Information
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Citation:
Li Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek, Hiroaki Kunieda,
"Motion Estimator LSI for MPEG2 High Level Standard,"
asp-dac,
p. 41,
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99),
1999
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