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Published Articles >> Table of Contents >> Abstract
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)
p. 33
The Design of Delay Insensitive Asynchronous 16-bit Microprocessor
Byung-Soo Choi, Kwang-Ju Institute of Science and Technology(K-JIST)
Dong-Wook Lee, Kwang-Ju Institute of Science and Technology(K-JIST)
Dong-Ik Lee, Kwang-Ju Institute of Science and Technology(K-JIST)
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759703
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| Abstract |
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In recent, asynchronous design has been
resurged to exploit potential advantages of asynchronous
VLSI such as; high-performance, low power consumption,
timing fault tolerance and design cost reduction.
This paper describes our first design and implementation
of DINAMIK project which aims to show realizability of
potential merits of asynchronous VLSI and to establish
the design methodology. In the design, ease of design(high
modularity) and delay insensitivity was especially emphasized
while power consumption, performance and area optimization
were ignored as the first stage of the project. To
achieve our main purpose simple architecture and a pessimistic
delay assumption has been selected. DINAMIK
has been fabricated as a SOG using 0.6 μ technology.
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 Additional Information
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Citation:
Byung-Soo Choi, Dong-Wook Lee, Dong-Ik Lee,
"The Design of Delay Insensitive Asynchronous 16-bit Microprocessor,"
asp-dac,
p. 33,
Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99),
1999
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