| Abstract |
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The benefits and costs of using merged arithmetic in the design of FIR lattice filters are investigated. The first design presented reduces hardware over the conventional lattice filter by combining the multiply and add operation into one block. The second design achieves a significant speed-up by deferring the carry-propagating addition until after the final lattice filter stage. This speed-up incurs a slight cost in additional hardware and additional wire communication between the lattice filter stages.
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 Additional Information
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Index Terms- FIR filters; lattice filters; digital arithmetic; adders; VLSI; multiplying circuits; high-speed VLSI implementation; FIR lattice filters design; merged arithmetic; multiply and add operation; speed-up; carry-propagating addition; hardware cost; wire communication; lattice filter stages
Citation:
K.A. Feiste, E.E. Swartzlander,
"High-speed VLSI implementation of FIR lattice filters,"
asilomar,
p. 127,
29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set),
1995
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