Published Articles >> Table of Contents >> Abstract

15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'04)   pp. 224-234
Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications
Zili Shao, University of Texas at Dallas
Qingfeng Zhuge, University of Texas at Dallas
Meilin Liu, University of Texas at Dallas
Bin Xiao, University of Texas at Dallas
Edwin H.-M. Sha, University of Texas at Dallas

Full Article Text:

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2004.10023
Send link to a friend

Abstract
This paper develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can greatly reduce both schedule length and bus switching activities compared with the previous work.
Back to Top Additional Information
Citation:  Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin H.-M. Sha, "Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications," asap, pp. 224-234,  15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'04),  2004