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Published Articles >> Table of Contents >> Abstract
14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03)
p. 348
Decimal Multiplication Via Carry-Save Addition
Mark A. Erle, Lehigh University
Michael J. Schulte, University of Wisconsin - Madison
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2003.1212858
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| Abstract |
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Decimal multiplication is important in many commercial applications including financial
analysis, banking, tax calculation, currency conversion, insurance, and accounting. This
paper presents two novel designs for fixed-point decimal multiplication that utilize decimal
carry-save addition to reduce the critical path delay. First, a multiplier that stores a reduced
number of multiplicand multiples and uses decimal carry-save addition in the iterative portion
of the design is presented. Then, a second multiplier design is proposed with several
notable improvements including fast generation of multiplicand multiples that do not need
be stored, the use of decimal (4:2) compressors, and a simplified decimal carry-propagate
addition to produce the final product. When multiplying two n-digit operands to produce a
2n-digit product, the improved multiplier design has a worst-case latency of n + 4 cycles
and an initiation interval of n + 1 cycles. Three data-dependent optimizations, which help
reduce the multipliers' average latency, are also described. The multipliers presented can be
extended to support decimal floating-point multiplication.
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 Additional Information
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Citation:
Mark A. Erle, Michael J. Schulte,
"Decimal Multiplication Via Carry-Save Addition,"
asap,
p. 348,
14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03),
2003
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