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Published Articles >> Table of Contents >> Abstract
14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03)
p. 337
Performance-Improved Computation of Very Large Word-Length LNS Addition/Subtraction Using Signed-Digit Arithmetic
Chichyang Chen, Department of Information Engineering and Computer Science
Rui-Lin Chen, Department of Information Engineering and Computer Science
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2003.1212857
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| Abstract |
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Pipelined computation of very large word-length LNS addition/subtraction requires a significant amount of hardware and long pipeline latency. In this paper, we propose a base- e exponential algorithm to simplify the exponential computation and to replace half of the pipeline stages by multiplication-and-accumulate operations. By using this approach, the circuit cost of the previously proposed 64-bit pipelined LNS addition/subtraction unit can be reduced by more than fifty percent. We also developed signed-digit (SD) algorithms to further enhance the performance of the LNS computation. From our analysis, the throughput of the 64-bit LNS unit can be increased by a factor of 4.62, and the pipeline latency can be reduced by a factor of seven. Furthermore, this SD approach can still save more than 50% of the table size and 27.6% of the circuit of the previously proposed LNS unit. The proposed approaches and algorithms have been verified by comprehensive simulations on the designed 32-bit SD hardware-reduced LNS unit. We have concluded that the proposed approaches can significantly improve the performance of very large word-length LNS addition/subtraction computation.
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 Additional Information
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Citation:
Chichyang Chen, Rui-Lin Chen,
"Performance-Improved Computation of Very Large Word-Length LNS Addition/Subtraction Using Signed-Digit Arithmetic,"
asap,
p. 337,
14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03),
2003
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