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Published Articles >> Table of Contents >> Abstract
14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03)
p. 194
A floating-point CORDIC based SVD processor
Z. Liu, DSiP Laboratories, Queen’s University of Belfast, Belfast, N. Ireland
K. Dickson, DSiP Laboratories, Queen’s University of Belfast, Belfast, N. Ireland
J. V. McCanny, DSiP Laboratories, Queen’s University of Belfast, Belfast, N. Ireland
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2003.1212843
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| Abstract |
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An SVD processor system is presented in which each processing element is implemented
using a simple CORDIC unit. The internal recursive loop within the CORDIC module is
exploited, with pipelining being used to multiplex the two independent micro-rotations onto a
single CORDIC processor. This leads to a high performance and efficient hardware
architecture. In addition, a novel method for scale factor correction is presented which only
need be applied once at the end of the computation. This also reduces the computation time.
The net result is an SVD architecture based on a conventional CORDIC approach, which
combines high performance with high silicon area efficiency.
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 Additional Information
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Citation:
Z. Liu, K. Dickson, J. V. McCanny,
"A floating-point CORDIC based SVD processor,"
asap,
p. 194,
14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03),
2003
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