| Abstract |
|
The demand for higher computing power to effectively execute compute-intensive functions and thus more on-chip computing resources is ever increasing. On the other hand, applications that demand larger on-chip
Memory bandwidth are continuously emerging. In this paper, we novel
on-chip processing element that leverages application-specific processing
capabilities. The ARC unit supplements a conventional register file to
provide large memory bandwidth, or acts as configurable computing
unit to provide higher on-chip computing capacity, depending on the
requirement of a specific application. When an out-of-order 8-wide
issue superscalar processor is supplemented with the ARC unit
to process matrix multiplication, a compute-intensive core function
.in most multimedia applications, results show a performance increase
of up to 12%. Similarly, a 9% performance enhancement is seen when
the matrix multiplication is performed in an out-of-order 4-wide issue
superscalar processor supplemented with the ARC unit. The paper
also discusses the microarchitecuture level details for the implementation
of the ARC unit.
|
 Additional Information
|
Index Terms- Memory bandwidth, Computing capacity, Register File, compute-intensive
Function.
Citation:
"Application-Specific Computing with Adaptive Register File Architectures,"
asap,
p. 183,
14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03),
2003
|
