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Published Articles >> Table of Contents >> Abstract
14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03)
p. 64
Systematic Register Bypass Customization for Application-Specific Processors
Kevin Fan, University of Michigan
Nathan Clark, University of Michigan
Michael Chu, University of Michigan
K. V. Manjunath, University of Michigan
Rajiv Ravindran, University of Michigan
Mikhail Smelyanskiy, University of Michigan
Scott Mahlke, University of Michigan
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2003.1212830
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| Abstract |
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Register bypass provides additional datapaths to eliminate data hazards in processor pipelines. The difficulty with register bypass is that the cost of the bypass network is substantial grows substantially as processor width or pipeline depth are increased. For a single application, many of the bypass paths have extremely low utilization. Thus, there is animportant opportunity in the design of application-specific processor to remove a largefraction of the bypass cost while maintaining performance comparable to a processorwith full bypass. This is end, we propose a systematic design customization processalong with a bypass-cognizant compiler scheduler. For the former, we employ iterative design space exploration wherein successive processor designs are selected based on bypass utilization statistic combined with availability of redundant bypass paths. Compiler scheduling for sparse bypass processors is accomplished by prioritizing function unit choices for each operation prior to scheduling using global information. Results show that for a 5-issue customized VLIW processor, 70% of the bypass cost is Eliminated while sacrificing only 10% performance.
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 Additional Information
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Citation:
Kevin Fan, Nathan Clark, Michael Chu, K. V. Manjunath, Rajiv Ravindran, Mikhail Smelyanskiy, Scott Mahlke,
"Systematic Register Bypass Customization for Application-Specific Processors,"
asap,
p. 64,
14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03),
2003
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