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Published Articles >> Table of Contents >> Abstract
14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03)
p. 40
Hardware Synthesis for Multi-Dimensional Time
Anne-Claire Guillou, Irisa Campus de Beaulieu
Patrice Quinton, Irisa Campus de Beaulieu
Tanguy Risset, Inria, Lip, ENS-Lyon
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2003.1212828
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| Abstract |
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This paper introduces some basic principles for extending the classical systolic synthesis
methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithms that do not admit linear schedules to be parallelized, but it also requires the use of
memories in the architecture. We explain how to obtain compatible allocation and memory
functions for vlsi (or simd-like code) generation. We also present an original mechanism
for controlling a vlsi architecture that has a multi-dimensional schedule. A structural vhdl
code has been derived and synthesized (for implementation on fpga platforms) using these
systematic design principles. These results are preliminary steps to the hardware synthesis
for multi-dimensional time.
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 Additional Information
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Index Terms- High-level synthesis, systolic architecture, multi-dimensional scheduling, fpga
Citation:
Anne-Claire Guillou, Patrice Quinton, Tanguy Risset,
"Hardware Synthesis for Multi-Dimensional Time,"
asap,
p. 40,
14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03),
2003
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