Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders

Vojin G. Oklobdzija; Bart R. Zeydel; Hoang Dao; Sanu Mathew; Ram Krishnamurthy

doi:10.1109/ARITH.2003.1207688

Proceedings. 16th IEEE Symposium on Computer Arithmetic

Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders

Year: 2003, Pages: 272

DOI Bookmark: 10.1109/ARITH.2003.1207688

Authors

Vojin G. Oklobdzija, University of California at Davis
Bart R. Zeydel, University of California at Davis
Hoang Dao, University of California at Davis
Sanu Mathew, Intel Corporation
Ram Krishnamurthy, Intel Corporation

Abstract

In this paper, we motivate the concept of comparing VLSI adders based on their energy-delay trade-offs and present a technique for estimating the energy-delay space of various high-performance VLSI adder topologies. Further, we show that our estimates accurately represent tradeoffs in the energy-delay space for high-performance 32-bit and 64-bit processor adders in 0.13 ?m and 0.10 ?m CMOS technologies, with an accuracy of 8% in delay estimates and 20% in energy estimates, compared with simulated data.

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Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders

Authors

Abstract

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