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Published Articles >> Table of Contents >> Abstract
16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03)
p. 87
High Performance Floating-Point Unit with 116 Bit Wide Divider
Guenter Gerwig, IBM Server Division
Holger Wetter, IBM Server Division
Eric M. Schwarz, IBM Server Division
Juergen Haess, IBM Server Division
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.2003.1207664
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The next generation zSeries floating-point unit is unveiled which is the first IBM mainframe with a fused multiply-add dataflow. It supports both S/390 hexadecimal floating-point architecture and the IEEE 754 binary floating-point architecture which was first implemented in S/390 on the 1998 S/390 G5 floating-point unit. The new floating-point unit supports a total of 6 formats including single, double, and quadword formats implemented in hardware. The floating-point pipeline is 5 cycles with a throughput of 1 multiply-add per cycle. Both hexadecimal and binary floating-point instructions are capable of this performance due to a novel way of handling both formats. Other key developments include new methods for handling denormalized numbers and quad precision divide engine dataflow. This divider Uses a radix-4 SRT algorithm and is able to handle quad precision divides in multiple floating-point and fixed-point formats. The number of iterations for fixed-point divisions depend on the effective number of quotient bits. It uses a reduced carry-save form for the partial remainder, with only 1 carry bit for every 4 sum bits, to save area and power.
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Citation:
Guenter Gerwig, Holger Wetter, Eric M. Schwarz, Juergen Haess,
"High Performance Floating-Point Unit with 116 Bit Wide Divider,"
arith,
p. 87,
16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03),
2003
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