Stacked capacitor cells for 64 MDRAM

Related Articles

• A 64 Mbit DRAM trench capacitor cell with field-plate isolation
  1991 International Symposium on VLSI Technology, Systems, and Applications
• A 58 ns 4 Mb CMOS DRAM with an effective one-shot gate address buffer
  International Symposium on VLSI Technology, Systems and Applications,
• A high quality stacked thermal/LPCVD gate oxide for ULSI
  1991 International Symposium on VLSI Technology, Systems, and Applications
• Centip3De: A 64-core, 3D stacked, near-threshold system
  2012 IEEE Hot Chips 24 Symposium (HCS)
• Design space exploration for 3D-stacked DRAMs
  Design, Automation & Test in Europe Conference & Exhibition
• Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
  2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
• A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• Centip3De: A 64-Core, 3D Stacked Near-Threshold System
  IEEE Micro
• CWFP: novel collective writeback and fill policy for last-level DRAM cache
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory
  IEEE Transactions on Computers