Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1

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July/August 2004 (Vol. 24, No. 4) pp. 33-41
Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1
Taeweon Suh, Georgia Institute of Technology
Hsien-Hsin S. Lee, Georgia Institute of Technology
Douglas M. Blough, Georgia Institute of Technology

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.33
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Abstract
This systematic methodology maintains cache coherency in a heterogeneous shared-memory multiprocessor system on a chip. It works with any combination of processors that support any invalidation-based protocol, and experiments have demonstrated up to a 51 percent performance improvement, compared to a pure software solution.
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Citation: Taeweon Suh, Hsien-Hsin S. Lee, Douglas M. Blough, "Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1," IEEE Micro, vol. 24, no. 4, pp. 33-41, Jul/Aug, 2004

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