QoS for High-Performance SMT Processors in Embedded Systems

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July/August 2004 (Vol. 24, No. 4) pp. 24-31
QoS for High-Performance SMT Processors in Embedded Systems
Francisco J. Cazorla, Polytechnic University of Catalonia
Alex Ramirez, Polytechnic University of Catalonia
Mateo Valero, Polytechnic University of Catalonia
Peter M.W. Knijnenburg, Leiden University
Rizos Sakellariou, University of Manchester
Enrique Fernández, University of Las Palmas de Gran Canaria

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.37
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Abstract
Although simultaneous multithreading processors provide a good cost-performance tradeoff, they exhibit unpredictable performance in real-time applications. The authors present a resource management scheme that eliminates a major cause of performance unpredictability in SMTs, making them suitable for many types of embedded systems.
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[1] T.R. Halfhill, "Philips Powers Up for Video," Microprocessor Report no. 168,, Nov.3, 2003. [2] M. Levy, "Multithreaded Technologies Disclosed at MPF," Microprocessor Report no. 168,, Nov.10, 2003. [3] R. Jain, C.J. Hughes, and S.V. Adve, "Soft Real-Time Scheduling on Simultaneous Multithreaded Processors," Proc. 23rd Real-Time Systems Symp. (RTSS-23), IEEE Press, 2002, pp. 134-145. [4] A. Snavely, D.M. Tullsen, and G. Voelker, "Symbiotic Job Scheduling with Priorities for a Simultaneous Multithreaded Processor," Proc. 9th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-9), ACM Press, 2000, pp. 234-244. [5] K. Luo, J. Gummaraju, and M. Franklin, "Balancing Throughput and Fairness in SMT Processors," Proc. IEEE Int'l. Symp. Performance Analysis of Systems and Software (ISPASS 01), IEEE Press, 2001, pp. 164-171. [6] F.J. Cazorla et al., "Approaching a Smart Sharing of Resources in SMT Processors," Proc. Workshop Complexity-Effective Design (WCED), June 2004; http://www.ece.rochester.edu/~albonesiwced04 /. [7] F.J. Cazorla et al., "Improving Memory Latency Aware Fetch Policies for SMT Processors," Proc. 5th Int'l Symp. High-Performance Computing (ISHPC-5), LNCS Press, 2003, pp. 70-85. [8] F.J. Cazorla et al., "DCache Warn: An I-Fetch Policy to Increase SMT Efficiency," Proc. 18th Int'l Parallel and Distributed Processing Symp. (IPDPS 04), IEEE CS Press, 2004, pp. 74-83. [9] D.M. Tullsen and P.J. Brown, Handling Long-Latency Loads in a Simultaneous Multithreading Processor Proc. 34th Int'l Symp. Microarchitecture, pp. 318-327, 2001. [10] P.M.W. Knijnenburg et al., "Branch classification for SMT fetch gating," 6th Workshop in Multi-Threaded Execution, Architecture and Compilation (MTEAC-6), 2002, pp. 49-56. [11] D. Tullsen et al., "Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor". Proc. 23rd Int'l Symp. on Computer Architecture (ISCA-23), 1996, pp. 191-202. [12] T. Sherwood, E. Perelman,, and B. Calder,"Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications," Proc. Int'l Conf. Parallel Architectures and Compilation Techniques, IEEE CS Press, 2001, pp 3-14. [13] F.J. Cazorla et al., "Predictable Performance in SMT Processors," Proc. 1st Conf. Computing Frontiers (CF 04), ACM Press, 2004, pp. 433-443.
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Citation: Francisco J. Cazorla, Alex Ramirez, Mateo Valero, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, "QoS for High-Performance SMT Processors in Embedded Systems," IEEE Micro, vol. 24, no. 4, pp. 24-31, Jul/Aug, 2004

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