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Published Articles >> Table of Contents >> Abstract
March/April 2004 (Vol. 24, No. 2)
pp. 40-47
IBM Power5 Chip: A Dual-Core Multithreaded Processor
Ron Kalla, IBM
Balaram Sinharoy, IBM
Joel M. Tendler, IBM
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.1289290
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| Abstract |
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Featuring single- and multithreaded execution, the Power5 provides higher performance in the single-threaded mode than its Power4 predecessor at equivalent frequencies. Enhancements include dynamic resource balancing to efficiently allocate system resources to each thread, software-controlled thread prioritization, and dynamic power management to reduce power consumption without affecting performance.
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 References
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[1] J.M. Tendler et al., "Power4 System Microarchitecture," IBM J. Research and Development, vol. 46, no. 1, Jan. 2002, pp. 5-26.
[2] J. Borkenhagen et al., "A Multithreaded Power PC Processor for Commercial Servers," IBM J. Research and Development, vol. 44, no. 6, Nov. 2000, pp. 885-898.
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[4] D.M. Tullsen, S.J. Eggers, and H.M. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism," Proc. 22nd Ann. Int'l Symp. Computer Architecture (ISCA 95), ACM Press, 1995, pp. 392-403.
[5] G.G. Shahidi et al., "Partially-Depleted SOI Technology for Digital Logic," Proc. Int'l Solid-State Circuits Conf. (ISSCC 99), IEEE Press, 1999, pp. 426-427.
[6] J.E. Smith, "A Study of Branch Prediction Strategies," Proc. 8th Int'l Symp. Computer Architecture (ISCA 81), IEEE CS Press, 1981, pp. 135-148.
[7] S. McFarling, Combining Branch Predictors, tech. note TN-36, Digital Equipment Corp. Western Research Laboratory, 1993.
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 Additional Information
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Citation:
Ron Kalla, Balaram Sinharoy, Joel M. Tendler,
"IBM Power5 Chip: A Dual-Core Multithreaded Processor,"
IEEE Micro,
vol. 24,
no. 2,
pp. 40-47,
Mar/Apr,
2004
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