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Published Articles >> Table of Contents >> Abstract
July/August 2003 (Vol. 23, No. 4)
pp. 32-42
A Programmable State Machine Architecture for Packet Processing
Wangyang Lai, Agere Systems
Chin-Tau Lea, Hong Kong University of Science and Technology
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2003.1225965
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| Abstract |
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Though complex and expensive, packet processors are programmable and can easily handle protocol changes. They are thus increasingly attractive for protocol processing.
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 References
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[1] "IBM PowerNP," http://www-3.ibm.com/chips/products/wired/ productsnetwork_processors.html.
[2] "Intel IXP1200 Network Processor," http://developer.intel.com/design/network/ products/npfamilyindex.htm.
[3] L. Gwennap, "Net Processor Makers Race Toward 10-Gbit/s Goal," EE Times,19 June 2000.
[4] D. Sherman, "SiPs Enable New Network Processors," EE Times,23 Nov. 2001.
[5] H. Shimonishi and T. Murase, "A Network Processor Architecture for Flexible QoS Control in Very High-Speed Line Interfaces," Proc. 2001 IEEE Workshop on High Performance Routing and Switching;http://engr.smu.edu/~tchenhpsr/.
[6] P. Alexander, "Application of Programmable Multithreaded Network Processor Architecture to OC-192 Packet Forwarding," Lexra Corp., 2001; http:/www.lexra.com.
[7] P.G. Paulin, F. Karim, and P. Bromley, "Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools," Proc. IEEE 2001 Design, Automation and Test in Europe, IEEE Press, 2001, pp 420-427.
[8] J.L. Hennessy and D.A. Patterson, Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann, 1997.
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 Additional Information
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Citation:
Wangyang Lai, Chin-Tau Lea,
"A Programmable State Machine Architecture for Packet Processing,"
IEEE Micro,
vol. 23,
no. 4,
pp. 32-42,
Jul/Aug,
2003
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