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Published Articles >> Table of Contents >> Abstract
January/February 2003 (Vol. 23, No. 1)
pp. 10-24
10 A Four-Terabit Packet Switch Supporting Long Round-Trip Times
Francois Abel, IBM Research, Zurich Research Laboratory
Cyriel Minkenberg, IBM Research, Zurich Research Laboratory
Ronald P. Luijten, IBM Research, Zurich Research Laboratory
Mitchell Gusat, IBM Research, Zurich Research Laboratory
Ilias Iliadis, IBM Research, Zurich Research Laboratory
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2003.1179894
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| Abstract |
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This 4-Tbps packet switch uses a combined input- and crosspoint-queued (CICQ) structure with virtual output queuing at the ingress to achieve the scalability of input-buffered switches, the performance of output-buffered switches, and low latency.
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 References
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[1] R. Rojas-Cessa, E. Oki, and H. Jonathan Chao, "CIXOB-k: Combined Input-Crosspoint-Output Buffered Packet Switch," Proc. IEEE Globecom 01, vol. 4,IEEE Press, 2001, pp. 2654-2660.
[2] J. Duato, S. Yalamanchili, and L.M. Ni, Interconnection Networks: An Engineering Approach. Morgan Kauffman, 2003.
[3] C. Minkenberg et al., "Current Issues in Packet Switch Design," HotNets-I 2002—First Workshop on Hot Topics in Networks, to be published in ACM SigComm Computer Comm. Rev., vol. 33, no. 1, Jan. 2003.
[4] N. McKeown, “The iSLIP Scheduling Algorithm for Input-Queued Switches,” IEEE/ACM Trans. Networking, vol. 7, no. 2, pp. 188-201, Apr. 1999.
[5] S. Chuang et al., Matching Output Queuing with a Combined Input Output Queued Switch IEEE J. Selected Areas in Comm., vol. 17, pp. 1030-1039, June 1999.
[6] P. Krishna et al., "On the Speedup Required for Work-Conserving Crossbar Switches," IEEE J. Selected Areas of Comm., vol. 17, no. 6, June 1999, pp. 1057-1066.
[7] M. Katevenis, D. Serpanos, and E. Spyridakis, Switching Fabrics with Internal Backpressure Using the ATLAS I Single-ChipATM Switch Proc. IEEE GLOBECOM'97, pp. 242-246, Nov. 1997.
[8] F.M. Chiussi, J.G. Kneuer, and V.P. Kumar, "Low-Cost Scalable Switching Solution for Broadband Networking: The ATLANTA Architecture and Chipset," IEEE Comm. Magazine, vol. 35, Dec. 1997, pp. 44-53.
[9] C. Minkenberg and T. Engbersen, "A Combined Input and Output Queued Packet-switched System Based on PRIZMA Switch-on-a-Chip Technology," IEEE Comm. Magazine, vol. 38, Dec. 2000, pp. 70-77.
[10] R.P. Luijten et al., "Optimized Architecture and Design of an Output-Queued CMOS Switch Chip," Proc. 10th Int'l Conf. Computer Communications and Networks, IEEE CS Press, 2001, pp. 448-453.
[11] D.C. Stephens and H. Zhang, “Implementing Distributed Packet Fair Queueing in Scalable Switch Architecture,” Proc. IEEE INFOCOM '98, pp. 282-290, Mar. 1998.
[12] M. Nabeshima, "Performance Evaluation of a Combined Input- and Crosspoint-Queued Switch," IEICE Trans. Communications, vol. E83-B, no. 3, Mar. 2000, pp. 737-741.
[13] T. Javidi, R. Magill, and T. Hrabik, "A High-Throughput Scheduling Algorithm for a Buffered Crossbar Switch Fabric," Proc. IEEE Int'l Conf. Communications, vol. 5, IEEE Press, 2001, pp. 1586-1591.
[14] A.K. Gupta, L. Orozco Barbosa, and N.D. Georganas, "16×16 Limited Intermediate Buffer Switch Module for ATM Networks," Proc. IEEE Globecom 91, IEEE Press, 1991, pp. 939-943.
[15] Y. Doi and N. Yamanaka, "A High-Speed ATM Switch with Input and Cross-Point Buffers," IEICE Trans. Communications, vol. E76-B, no. 3, Mar. 1993, pp. 310-314.
[16] M. Gusat et al., "Stability Degree of Switches with Finite Buffers under Non-Negligible RTT," Microprocessor and Microsystems J., Elsevier Press, to be published 2003.
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 Additional Information
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Citation:
Francois Abel, Cyriel Minkenberg, Ronald P. Luijten, Mitchell Gusat, Ilias Iliadis,
"10 A Four-Terabit Packet Switch Supporting Long Round-Trip Times,"
IEEE Micro,
vol. 23,
no. 1,
pp. 10-24,
Jan/Feb,
2003
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