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Published Articles >> Table of Contents >> Abstract
November/December 2002 (Vol. 22, No. 6)
pp. 58-69
Data Communication in Systems with Heterogeneous Timing
Fei Xia
Alex V. Yakovlev
Ian G. Clark
Delong Shang
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2002.1134344
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| Abstract |
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Asynchronous communication mechanisms permit the implementation of data interfaces between heterogeneously timed entities at various hardware levels. A systematic approach to ACM classification, specification, and implementation facilitates their use in heterogeneously timed networks.
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 References
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[1] L. Lamport, "On Interprocess Communication: Parts I and II," Distributed Computing, vol. 1, no. 2, 1986, pp. 77-101.
[2] H. Simpson, “Four-Slot Fully Asynchronous Communication Mechanism,” IEE Proc, vol. 137,no. Py. E 1, pp. 17-30, Jan. 1990.
[3] H.R. Simpson and E. Campbell, "Real-Time Network Architecture: Principles and Practice," Proc. Asynchronous Interfaces: Tools, Techniques and Implementations (AINT 00), Technische Universiteit Delft, the Netherlands, 2000, p. 5 and handouts.
[4] D.M. Chapiro, Globally-Asynchronous Locally-Synchronous Systems, doctoral dissertation, Dept. of Computer Science, Stanford Univ., Palo Alto, Calif., 1986.
[5] K.Y. Yun and A.E. Dooply, "Pausible Clocking Based Heterogeneous Systems," IEEE Trans. Very Large-Scale Integration (VLSI) Systems, vol. 7, no. 4, Dec. 1999, pp. 482-488.
[6] T. Chelcea and S. Novick, "Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols," Proc. 38th Design Automation Conf. (DAC 01), ACM Press, New York, 2001, pp. 21-26.
[7] L.P. Carloni, K.L. McMillan, and A.L. Sangiovanni-Vincentelli, "Theory of Latency-Insensitive Design," IEEE Trans. Computer-Aided Design, vol. 20, no. 9, Sept. 2001, pp. 1059-1076.
[8] J.L. Peterson, Petri Net Theory and the Modeling of Systems.Englewood Cliffs, N.J.: Prentice Hall, 1981.
[9] F. Xia et al., "Asynchronous Communication Mechanisms Using Self-Timed Circuits," Proc. 6th Int'l Symp. Advanced Research Asynchronous Circuits and Systems (ASYNC 00), IEEE CS Press, Los Alamitos, Calif., 2000, pp. 150-159.
[10] A. Yakovlev, F. Xia, and D. Shang, "Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism," Proc. 7th Int'l Symp. Asynchronous Circuits and Systems (ASYNC 01), IEEE CS Press, Los Alamitos, Calif., 2001, pp. 127-136.
[11] F. Xia and I. Clark, "Algorithms for Signal and Message Asynchronous Communication Mechanisms and Their Analysis," Proc. 2nd Int'l Conf. Applications of Concurrency to System Design (ACSD 01), IEEE CS Press, Los Alamitos, Calif., 2001, pp. 65-74.
[12] D. Shang, F. Xia, and A. Yakovlev, "Asynchronous Circuit Synthesis via Direct Translation," Proc. Int'l Symp. Circuits and Systems (ISCAS 02), IEEE Press, Piscataway, N.J., 2002, pp. 369-372.
[13] D. Shang, F. Xia, and A. Yakovlev, "Testing a Self-Timed Asynchronous Communication Mechanism (ACM) VLSI Chip," IEEE Workshop Design and Diagnostics of Electronic Circuits and Systems (DDECS 01), IEEE Press, Piscataway, N.J., 2001, pp. 53-56.
[14] A. Madalinski, F. Xia, and A. Yakovlev, "Studying the Data Loss and Data Re-Reading Behaviour of a Four-Slot ACM Using SPN Techniques," Proc. 7th UK Async Forum, 1999; http://www.cs.man.ac.uk/async/eventsukforum.html .
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 Additional Information
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Citation:
Fei Xia, Alex V. Yakovlev, Ian G. Clark, Delong Shang,
"Data Communication in Systems with Heterogeneous Timing,"
IEEE Micro,
vol. 22,
no. 6,
pp. 58-69,
Nov/Dec,
2002
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