Scaling to the End of Silicon with EDGE Architectures

Published Articles >> Table of Contents >> Abstract

July 2004 (Vol. 37, No. 7) pp. 44-55
Scaling to the End of Silicon with EDGE Architectures
Doug Burger, The University of Texas at Austin
Stephen W. Keckler, The University of Texas at Austin
Kathryn S. McKinley, The University of Texas at Austin
Mike Dahlin, The University of Texas at Austin
Lizy K. John, The University of Texas at Austin
Calvin Lin, The University of Texas at Austin
Charles R. Moore, The University of Texas at Austin
James Burrill, The University of Texas at Austin
Robert G. McDonald, The University of Texas at Austin
William Yoder, The University of Texas at Austin
the TRIPS Team, The University of Texas at Austin

Full Article Text:

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MC.2004.65
Send link to a friend

Abstract
Post-RISC microprocessor designs must introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible. To meet these challenges, the TRIPS Team at the University of Texas at Austin has developed a new class of ISAs, called Explicit Data Graph Execution, that will match the characteristics of semiconductor technology over the next decade. EDGE architectures appear to offer a progressively better solution as technology scales down to the end of silicon, with each generation providing a richer spatial substrate at the expense of increased global communication delays.
About References \| Back to Top References
[1] M.S. Hrishikesh et al., "The Optimal Logic Depth per Pipeline Stage Is 6 to 8 fo4 Inverter Delays," Proc. 29th Int'l Symp. Computer Architecture (ISCA 02), IEEE CS Press, 2002, pp. 14-24. [2] S.A. Mahlke et al., "Effective Compiler Support for Predicated Execution Using the Hyperblock," Proc. 25th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-25), IEEE CS Press, 1992, pp. 45-54. [3] R.A. Chowdhury et al., "The Limits of Alias Analysis for Scalar Optimizations," Proc. ACM SIGPLAN 2004 Conf. Compiler Construction, ACM Press, 2004, pp. 24-38. [4] K. Sankaralingam et al., "Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture," Proc. 30th Int'l Symp. Computer Architecture (ISCA 03), IEEE CS Press, 2003, pp. 422-433. [5] K. Sankaralingam et al., "Universal Mechanisms for Data-Parallel Architectures," Proc. 36th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-36), IEEE CS Press, 2003, pp. 303-314. [6] D.M. Tullsen, S.J. Eggers, and H.M. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism," Proc. 22nd Int'l Symp. Computer Architecture (ISCA 95), IEEE CS Press, 1995, pp. 392-403. [7] K. Olukotun et al., "The Case for a Single-Chip Multiprocessor," Proc. 6th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 94), ACM Press, 1994, pp. 2-11. [8] K. Mai et al., "Smart Memories: A Modular Reconfigurable Architecture," Proc. 27th Int'l Symp. Computer Architecture (ISCA 00), IEEE CS Press, 2000, pp. 161-171. [9] S. Rixner et al., "A Bandwidth-Efficient Architecture for Media Processing," Proc. 31st Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-31), IEEE CS Press, 1998, pp. 3-13. [10] E. Waingold et al., "Baring It All to Software: RAW Machines," Computer, Sept. 1997, pp. 86-93. Additional References [1] J.A. Fisher et al., "Parallel Processing: A Smart Compiler and a Dumb Machine," Proc. 1984 SIGPLAN Symp. Compiler Construction, ACM Press, 1984, pp. 37-47. [2] K.I. Farkas et al., "The Multicluster Architecture: Reducing Cycle Time Through Partitioning," Proc. 30th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-30), IEEE CS Press, 1997, pp. 149-159. [3] G.S. Sohi, S.E. Breach, and T.N. Vijaykumar, "Multiscalar Processors," Proc. 22nd Int'l Symp. Computer Architecture (ISCA 95), IEEE CS Press, 1995, pp. 414-425. [4] Arvind, "Data Flow Languages and Architecture," Proc. 8th Int'l Symp. Computer Architecture (ISCA 81), IEEE CS Press, 1981, p. 1. [5] H.T. Kung, "Why Systolic Architectures?" Computer, Jan. 1982, pp. 37-46.
Back to Top Additional Information
Citation: Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Mike Dahlin, Lizy K. John, Calvin Lin, Charles R. Moore, James Burrill, Robert G. McDonald, William Yoder, the TRIPS Team, "Scaling to the End of Silicon with EDGE Architectures," Computer, vol. 37, no. 7, pp. 44-55, Jul., 2004

RSS Feed

	Advanced Search
CS Search Google Search