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Published Articles >> Table of Contents >> Abstract
April 2000 (Vol. 33, No. 4)
pp. 41-49
The Density Advantage of Configurable Computing
Andre DeHon
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/2.839320
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More and more, field-programmable gate arrays (FPGAs) are accelerating computing applications. The absolute performance achieved by these configurable machines has been impressive--often one to two orders of magnitude greater than processor-based alternatives. Configurable computing is one of the fastest, most economical ways to solve problems such as RSA (Rivest-Shamir-Adelman) decryption, DNA sequence matching, signal processing, emulation, and cryptographic attacks. But questions remain as to why FPGAs have been so much more successful than their microprocessor and DSP counterparts. Do FPGA architectures have inherent advantages? Or are these examples just flukes of technology and market pricing? Will advantages increase, decrease, or remain the same as technology advances? Is there some generalization that accounts for the advantages in these cases? The author attempts to answer these questions and to see how configurable computing fits into the arsenal of structures used to build general, programmable computing platforms.
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 References
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[1] S. Knapp, Using Programmable Logic to Accelerate DSP Functions, Xilinx Inc., San Jose, Calif., Mar. 1998; http://www.xilinx.com/appnotesdspintro.pdf .
[2] M. Butts, "Future Directions of Dynamically Reprogrammable Systems," Proc. 1995 IEEE Custom Integrated Circuits Conf., IEEE CS Press, Los Alamitos, Calif., 1995, pp. 487-494.
[3] I. Goldberg and D. Wagner, Architectural Considerations for Cryptanalytic Hardware, Report CS252, Univ. of California, Berkeley, 1996; http://www.cs.berkeley.edu/~iang/isaachardware /.
[4] P.E. Gronowski et al., "A 433mhz 64b Quad-Issue RISC Microprocessor," Proc. Int'l Solid-State Circuit Conf., IEEE, 1996, pp. 182-223.
[5] W. Tsu et al., "HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array," Proc. Int'l Symp. Field-Programmable Gate Arrays, IEEE CS Press, Los Alamitos, Calif., 1999, pp. 125-134.
[6] A. DeHon, “Architectures for General-Purpose Computing,” A.I. Technical Report No. 1586, Artificial Intelligence Laboratory, MIT, Oct. 1996.
[7] J. Fadavi-Ardekani, "M×N Booth Encoded Multiplier Generator Using Optimized Wallace Trees," IEEE Trans. VLSI Systems, June 1993, pp. 120-125.
[8] T. Isshiki and W.W.-M. Dai, "High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems," Proc. ACM/ SIGDA Int'l Symp. Field-Programmable Gate Arrays, ACM Press, New York, 1995, pp. 167-173.
[9] K. Kaneko et al., "A 50ns DSP with Parallel Processing Architecture," Digest of Tech. Papers, 1987 Int'l Solid-State Circuits Conf., IEEE Press, Piscataway, N.J., 1987, pp. 158-159.
[10] J. Yetter et al., "A15-MIPS 32b Microprocessor," Digest of Tech. Papers, 1987 Int'l Solid-State Circuits Conf., IEEE Press, Piscataway, N.J., 1987, pp. 26-27.
[11] D.J. Magenheimer et al., "Integer Multiplication and Division on the HP Precision Architecture," Proc. Second Int'l Conf. Architectural Support for Programming Languages and Operating Systems, IEEE Press, Piscataway, N.J., 1987, pp. 90-99.
[12] K.D. Chapman, "Fast Integer Multipliers Fit in FPGAs," EDN, Vol. 39, No. 10, May12, 1993, p. 80.
[13] K. Nadehara, M. Hayashida, and I. Kuroda, "A Low-Power, 32-bit RISC Processor with Signal Processing Capability and Its Multiply-Adder," VLSI Signal Processing, IEEE Press, Piscataway, N.J., 1995, pp.51-60.
[14] B. Newgard, "Signal Processing with Xilinx FPGAs," 1996; http://www.xilinx.com/apps/appnotessd_xdsp.pdf .
[15] Implementing FIR Filters in FLEX Devices, Altera Corp., San Jose, Calif., 1998; http://www.altera.com/document/anan073.pdf .
[16] P. Ruetz, "The Architectures and Design of a 20-MHz Real-Time DSP Chip Set," IEEE J. Solid-State Circuits, Apr. 1989, pp. 338-348.
[17] C. Golla et al., "30MSamples/s Programmable Filter Processor," IEEE J. Solid-State Circuits, Dec. 1990, pp. 1502-1509.
[18] D. Reuver and H. Klar, "A Configurable Convolution Chip with Programmable Coefficients," IEEE J. Solid-State Circuits, July 1992, pp. 1121-1123.
[19] J. Laskowski and H. Samueli, "A 150-MHz 43-Tap Half-Band FIR Digital Filter in 1.2-μm CMOS Generated by Silicon Compiler," Proc. Custom Integrated Circuits Conf., IEEE Press, Piscataway, N.J., 1992, pp. 11.4.1-11.4.4.
Additional References
[1] J.S. Rose et al., "Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency," IEEE J. Solid-State Circuits, Vol. 25, No. 5, Oct. 1990, pp. 1217-1225.
[2] Field-Programmable Gate Array Technology, S.M. Trimberger, ed. Boston: Kluwer Academic, 1994.
Additional References
[1] A. DeHon, “Architectures for General-Purpose Computing,” A.I. Technical Report No. 1586, Artificial Intelligence Laboratory, MIT, Oct. 1996.
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 Additional Information
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Citation:
Andre DeHon,
"The Density Advantage of Configurable Computing,"
Computer,
vol. 33,
no. 4,
pp. 41-49,
Apr.,
2000
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